Instrukcja obsługi Texas Instruments SN74LVC2G157DCUR

Texas Instruments nieskategoryzowany SN74LVC2G157DCUR

Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Texas Instruments SN74LVC2G157DCUR (27 stron) w kategorii nieskategoryzowany. Ta instrukcja była pomocna dla 20 osób i została oceniona przez 2 użytkowników na średnio 4.5 gwiazdek

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G157

SCES207N – APRIL 1999 – REVISED MARCH 2019

SN74LVC2G157 Single 2-Line to 1-Line data selector multiplexer

1 Features

• Available in the Texas Instruments

NanoFree™ package

• Supports 5-V VCC operation

• Inputs accept voltages to 5.5 V

• Max tpd of 6 ns at 3.3 V

• Low power consumption, 10-µA Maximum I CC

• ±24-mA Output drive at 3.3 V

• Typical VOLP (Output ground bounce)

<0.8 V at VCC = 3.3 V, TA= 25°C

• Typical VOHV (Output VOH undershoot)

>2 V at VCC = 3.3 V, TA= 25°C

• Io Supports live insertion, partial-power-down

mode, and back-drive protection

• Can be used as a down translator to translate

inputs from a maximum of 5.5 V down

to the VCC Level

• Latch-up performance exceeds 100 mA per

JESD 78, Class II

• ESD Protection exceeds JESD 22

– 2000-V Human body model (A114-A)

– 1000-V Charged-device model (C101)

2 Applications

• Barcode scanner

• Cable solutions

• E-books

• Embedded PC

• Field transmitter: temperature or pressure sensors

• Fingerprint biometrics

• HVAC: Heating, ventilating, and air conditioning

• Network-attached storage (NAS)

• Server motherboard and PSU

• Software dened radio (SDR)

• TV: High denition (HDTV), LCD, and digital

• Video communications systems

• Wireless data access cards, headsets, keyboards,

mice, and LAN cards

3 Description

This single 2-line to 1-line data selector multiplexer is

designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G157 device features a common

strobe (G) input. When the strobe is high, Y is low

and Y is high. When the strobe is low, a single bit is

selected from one of two sources and is routed to the

outputs. The device provides true and complementary

data.

NanoFree™ package technology is a major

breakthrough in IC packaging concepts, using the die

as the package.

This device is fully specied for partial-power-down

applications using Io. The Io circuitry disables the

outputs, preventing damaging current backow

through the device when it is powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN74LVC2G157DCT SSOP (8) 2.95 mm × 2.80 mm

SN74LVC2G157DCU VSSOP (8) 2.30 mm × 2.00 mm

SN74LVC2G157YZP DSBGA (8) 1.91 mm × 0.91 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)

SN74LVC2G157

SCES207N –APRIL 1999 – REVISED MARCH 2019

www.ti.com

Product Folder Links: SN74LVC2G157

Table of Contents

1 Features .................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Conguration and Functions ......................... 3

6 Specications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions ...................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics .......................................... 5

6.6 Switching Characteristics ......................................... 6

6.7 Operating Characteristics.......................................... 6

6.8 Typical Characteristics .............................................. 6

7 Parameter Measurement Information .................. 7

8 Detailed Description .............................................. 8

8.1 Overview ................................................................... 8

8.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 8

8.4 Device Functional Modes.......................................... 9

9 Application and Implementation ........................ 10

9.1 Application Information............................................ 10

9.2 Typical Application ................................................. 10

10 Power Supply Recommendations ..................... 12

11 Layout................................................................... 12

11.1 Layout Guidelines ................................................. 12

11.2 Layout Example .................................................... 13

12 Device and Documentation Support ................. 14

12.1 Documentation Support ........................................ 14

12.2 Community Resources.......................................... 14

12.3 Trademarks ........................................................... 14

12.4 Electrostatic Discharge Caution ............................ 14

12.5 Glossary ................................................................ 14

13 Mechanical, Packaging, and Orderable

Information ........................................................... 14

4 Revision History

NOTE: Page numbers for previous revisions may dier from page numbers in the current version.

Changes from Revision M (June 2015) to Revision N Page

• Changed YZP package pinout drawing to match mechanical data drawing; and, pin functions description for clarity ........ 3

• Added additional thermal metrics for all packages................................................................................................................. 5

• Added detailed feature description sections for Standard CMOS Inputs, Balanced High-Drive CMOS Push-Pull

Outputs, and Negative Clamping Diodes. .............................................................................................................................. 8

• Added improved Design Requirements and Detailed Design Procedure............................................................................. 10

• Changed verbiage to better reect recommendations for this specic device rather than logic devices in general............ 12

• Added layout example for the YZP package. ....................................................................................................................... 12

Changes from Revision L (January 2014) to Revision M Page

• Added table.......................................................................................................................................................ESD Ratings 4

• Added ..........................................................................................................................................Thermal Information table. 5

• Added ................................................................................................................................................Typical Characteristics 6

• Added section.....................................................................................Mechanical, Packaging, and Orderable Information 14

Changes from Revision K (January 2007) to Revision L Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed table .....................................................................................................................................Ordering Information 1

• Updated ...................................................................................................................................................................Features 1

• Added table .............................................................................................................................................Device Information 1

GND Y

Y A/B

VCC

4 5

A VCC

GND

Y A/B

A/B

A VCC

GND

SN74LVC2G157

www.ti.com

SCES207N – APRIL 1999 – REVISED MARCH 2019

Product Folder Links: SN74LVC2G157

Submit Documentation Feedback

5 Pin Conguration and Functions

DCT Package

8-Pin SSOP

Top View

DCU Package

8-Pin VSSOP

Top View

YZP Package

8-Pin DSBGA

Bottom View

Drawing are not to scale. See mechanical drawings for dimensions

Pin Functions

I/O DESCRIPTION

NAME SSOP,

VSSOP DSBGA

A 1 A1 Input Data Input A

A/B 6 C2 Input Input Selector

B 2 B1 Input Data Input B

G 7 B2 Input Common Strobe Input

GND 4 D1 — Ground

VCC 8 A2 — Positive Supply

Y 5 D2 Output Output

Y 3 C1 Output Inverted Output

Specyfikacje produktu

Marka:	Texas Instruments
Kategoria:	nieskategoryzowany
Model:	SN74LVC2G157DCUR
Wysokość produktu:	0.8 mm
Szerokość produktu:	2.1 mm
Głębokość produktu:	2.4 mm
Szerokość opakowania:	180 mm
Wysokość opakowania:	18 mm
Głębokość opakowania:	180 mm
Ilość na paczkę:	3000 szt.
Zakres temperatur (eksploatacja):	-40 - 85 °C
Liczba styków:	8
Zakres temperatur (przechowywanie):	-65 - 150 °C
Model:	Logiczny układ scalony
Rodzaj opakowania:	VSSOP
Szerokość (z bolcami):	2.1 mm
Głębokość (z bolcami):	3.2 mm
Wysokość (z bolcami):	0.9 mm