Instrukcja obsługi Intel SL22U

Intel edytor SL22U

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Intel® 64 Architecture x2APIC
Specification
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ReReference Number: 318148-004
ference Number: 318148-004
ference Number: 318148-004
ference Number: 318148-004ference Number: 318148-004
March 2010
March 2010
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FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
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Developers must not rely on the absence or characteristics of any features or instructions marked “re-
served” or “undefined. Improper use of reserved or undefined features or instructions may cause unpre-
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or incompatibilities arising from their unauthorized use.
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Technology-enabled BIOS and VMM applications are currently in development.
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ating system, device drivers and applications enabled for Intel ® 64 architecture. Processors will not operate
(including 32-bit operation) without an Intel ® 64 architecture-enabled BIOS. Performance will vary de-
pending on your hardware and software configurations. Consult with your system vendor for more infor-
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Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
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or visit Intel’s website at http://www.intel.com
Copyright © 2006-2010 Intel Corporation
1-1
INTRODUCTION
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION
The xAPIC architecture provided a key mechanism for interrupt delivery in many
generations of Intel processors and platforms across different market segments. This
document describes the x2APIC architecture which is extended from the xAPIC archi-
tecture (the latter was first implemented on Intel® Pentium® 4 Processors, and
extended the APIC architecture implemented on Pentium and P6 processors). Exten-
sions to the xAPIC architecture are intended primarily to increase processor addres-
sability. The x2APIC architecture provides backward compatibility to the xAPIC
architecture and forward extendability for future Intel platform innovations. Specifi-
cally, x2APIC
Retains all key elements of compatibility to the xAPIC architecture:
delivery modes,
interrupt and processor priorities,
interrupt sources,
interrupt destination types;
Provides extensions to scale processor addressability for both the logical and
physical destination modes;
Adds new features to enhance performance of interrupt delivery;
Reduces complexity of logical destination mode interrupt delivery on link based
architectures.
1.2 IMPACTED PLATFORM COMPONENTS
x2APIC is architected to extend from the xAPIC architecture while minimizing the
impact on platform components. Specifically, support for the x2APIC architecture can
be implemented in the local APIC unit. All existing PCI/MSI capable devices and
IOxAPIC unit should work with the x2APIC extensions defined in this document. The
x2APIC architecture also provides flexibility to cope with the underlying fabrics that
connect the PCI devices, IOxAPICs and Local APIC units.
The extensions provided in this specification translate into modifications to:
the local APIC unit,
the underlying fabrics connecting Message Signaled Interrupts (MSI) capable PCI
devices to local xAPICs,
the underlying fabrics connecting the IOxAPICs to the local APIC units.


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