Instrukcja obsล‚ugi Texas Instruments SN74CBTLV3251DR

Texas Instruments Niesklasyfikowane SN74CBTLV3251DR

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๎˜๎˜‚๎˜ƒ๎˜„๎˜…๎˜†๎˜‡๎˜ˆ๎˜‰๎˜Š๎˜‹๎˜Œ๎˜
๎˜ˆ๎˜Ž๎˜๎˜๎˜‰๎˜Ž๎˜ˆ๎˜‡๎˜‘๎˜’๎˜“ ๎˜๎˜๎˜Ž๎˜”๎˜๎˜• ๎˜”๎˜“๎˜‡ ๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›๎˜œ๎˜๎˜“๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›
SCDS054I โˆ’ MARCH 1998 โˆ’ REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 โ€ข DALLAS, TEXAS 75265
D5-โ„ฆ Switch Connection Between Two Ports
DRail-to-Rail Switching on Data I/O Ports
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B4
B3
B2
B1
A
NC
OE
GND
VCC
B5
B6
B7
B8
S0
S1
S2
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
NC โˆ’ No internal connection
RGY PACKAGE
(TOP VIEW)
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
B5
B6
B7
B8
S0
S1
B3
B2
B1
A
NC
OE
B4
S2 V
GND
CC
NC โˆ’ No internal connection
description/ordering information
The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select inputs (S0, S1, S2) control the data ๎‹Šow. The FET multiplexers/demultiplexers are disabled when
the output-enable (OE) input is high.
This device is fully speci๎‹‰ed for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
APACKAGEโ€ ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN โˆ’ RGY Tape and reel SN74CBTLV3251RGYR CL251
SOIC D
Tube SN74CBTLV3251D
CBTLV3251
40ยฐ ยฐC to 85 C
SOIC โˆ’ D Tape and reel SN74CBTLV3251DR CBTLV3251
โˆ’40ยฐ ยฐC to 85 C SSOP (QSOP) โˆ’ DBQ Tape and reel SN74CBTLV3251DBQR CL251
TSSOP โˆ’ PW Tape and reel SN74CBTLV3251PWR CL251
TVSOP โˆ’ DGV Tape and reel SN74CBTLV3251DGVR CL251
โ€ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright ๏ฃฉ 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
๎˜™๎˜›๎˜Ž๎˜๎˜—๎˜…๎˜‡๎˜˜๎˜Ž๎˜‚ ๎˜๎˜‘๎˜‡๎˜‘ ๎˜ž๎˜Ÿ!"#$%&๎˜ž"๎˜Ÿ ๎˜ž' ()##*๎˜Ÿ& %' "! +),-๎˜ž(%&๎˜ž"๎˜Ÿ .%&*/
๎˜™#".)(&' ("๎˜Ÿ!"#$ &" '+*(๎˜ž!๎˜ž(%&๎˜ž"๎˜Ÿ' +*# &0* & *#$' "! ๎˜‡*1%' ๎˜˜๎˜Ÿ'&#)$*๎˜Ÿ&'
'&%๎˜Ÿ.%#. 2%##%๎˜Ÿ&3/ ๎˜™#".)(&๎˜ž"๎˜Ÿ +#"(*''๎˜ž๎˜Ÿ4 ."*' ๎˜Ÿ"& ๎˜Ÿ*(*''%#๎˜ž-3 ๎˜ž๎˜Ÿ(-).*
&*'&๎˜ž๎˜Ÿ4 "! %-- +%#%$*&*#'/
๎˜๎˜‚๎˜ƒ๎˜„๎˜…๎˜†๎˜‡๎˜ˆ๎˜‰๎˜Š๎˜‹๎˜Œ๎˜
๎˜ˆ๎˜Ž๎˜๎˜๎˜‰๎˜Ž๎˜ˆ๎˜‡๎˜‘๎˜’๎˜“ ๎˜๎˜๎˜Ž๎˜”๎˜๎˜• ๎˜”๎˜“๎˜‡ ๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›๎˜œ๎˜๎˜“๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›
SCDS054I โˆ’ MARCH 1998 โˆ’ REVISED OCTOBER 2003
2POST OFFICE BOX 655303 โ€ข DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
OE S2 S1 S0
FUNCTION
L L L L A port = B1 port
L L L H A port = B2 port
L L H L A port = B3 port
L L H H A port = B4 port
L H L L A port = B5 port
L H L H A port = B6 port
L H H L A port = B7 port
L H H H A port = B8 port
H X X X Disconnect
logic diagram (positive logic)
B5
B1
A
S0
S1
S2
OE
B2
B3
B4
B6
B7
B8
SW
SW
SW
SW
SW
SW
SW
SW
5
11
10
9
7
4
3
2
1
15
14
13
12
๎˜๎˜‚๎˜ƒ๎˜„๎˜…๎˜†๎˜‡๎˜ˆ๎˜‰๎˜Š๎˜‹๎˜Œ๎˜
๎˜ˆ๎˜Ž๎˜๎˜๎˜‰๎˜Ž๎˜ˆ๎˜‡๎˜‘๎˜’๎˜“ ๎˜๎˜๎˜Ž๎˜”๎˜๎˜• ๎˜”๎˜“๎˜‡ ๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›๎˜œ๎˜๎˜“๎˜–๎˜—๎˜ˆ๎˜‡๎˜˜๎˜™๎˜ˆ๎˜“๎˜š๎˜“๎˜›
SCDS054I โˆ’ MARCH 1998 โˆ’ REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 โ€ข DALLAS, TEXAS 75265
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) โ€ 
Supply voltage range, VCC โˆ’0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) โˆ’0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IK (VI/O < 0) โˆ’50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, ฮธJA (see Note 2): D package 73ยฐC/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DBQ package 90ยฐC/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 120ยฐC/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 108ยฐC/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 39ยฐC/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg โˆ’65ยฐ ยฐC to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
โ€ Stresses beyond those listed under โ€œabsolute maximum ratingsโ€ may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under โ€œrecommended operating conditionsโ€ is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
V
High level control input voltage
VCC = 2.3 V to 2.7 V 1.7
V
VIH High-level control input voltage VCC = 2.7 V to 3.6 V 2 V
V
L l l t l i t lt
VCC = 2.3 V to 2.7 V 0.7
V
VIL Low-level control input voltage VCC = 2.7 V to 3.6 V 0.8 V
TAOperating free-air temperature โˆ’40 85 Cยฐ
NOTE 4: All unused control inputs of the device must be held at V
CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Specyfikacje produktu

Marka: Texas Instruments
Kategoria: Niesklasyfikowane
Model: SN74CBTLV3251DR

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