Instrukcja obsługi Microchip SY89851U


Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Microchip SY89851U (12 stron) w kategorii nieskategoryzowany. Ta instrukcja była pomocna dla 12 osób i została oceniona przez 2 użytkowników na średnio 4.5 gwiazdek

Strona 1/12
SY89851U
Low Power, 3GHz, 1:2 LVPECL Fanout
Buffer/Translator with Internal Termination
July 2005 M9999-071205
hbwhelp@micrel.com -or (408) 955 1690
General Description
The SY89851U is a low jitter, low skew, high-speed
1:2 differential fanout buffer optimized for precision
telecom and enterprise server distribution
applications. The SY89851U distributes clock
frequencies from DC to >3GHz, and data rates to
2.5Gbps guaranteed over temperature and voltage.
The SY89851U differential input includes Micrel's
unique, 3-pin input termination architecture that
directly interfaces to any differential signal (AC- or
DC-coupled) as small as 100mV (200mVpp) without
any level shifting or termination resistor networks in
the signal path. The outputs are 800mV, 100K-
compatible LVPECL with extremely fast rise/fall time
guaranteed to be less than 180ps.
The SY89851U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of 40°C to +8C. The
SY89851U is part of Micrel's high speed, Precision -
Edge® product line.
All support documentation can be found on Micrel's
web site at www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
Precision 1:2, 800mV LVPECL fanout buffer
Low power consumption: 80mW typ. (2.5V)
Guaranteed AC performance over temperature
and voltage:
DC to >3GHz clock throughput
<340ps propagation delay
<180ps rise/fall time
- -<20ps output to output skew
Ultra-low jitter design:
– <1psRMS random jitter
– <10psPP deterministic jitter
– <10psPP total jitter (clock)
Unique, patented input termination and VT pin
accepts DC and AC coupled inputs (CML,- -
LVPECL, LVDS)
100K LVPECL-compatible outputs
Power supply 2.5V ± ±5% or 3.3V 10%
–40°C to +85°C industrial temperature range
Available in 16-pin (3mm x 3mm) QFN package
Applications
All SONET and GigE clock distribution
Fibre Channel applications
Backplane distribution
High-end, low skew, multiprocessor synchronous
clock distribution
Precisi Edge is egisteron a r
ed trademark f icrel, Inc. o M
Micrel, Inc. SY89851U
July 2005 - M9999 071205
hbwhelp@micrel.com -or (408) 955 1690
2
Ordering Information(1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY89851UMG 16 -QFN Industrial 851U with
Pb- -Free bar line indicator
Pb-Free
NiPdAU
SY89851UMGTR(2) - QFN 16 Industrial 851U with
Pb- -Free bar line indicator
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Conguration
16-Pin QFN
Micrel, Inc. SY89851U
July 2005 - M9999 071205
hbwhelp@micrel.com -or (408) 955 1690
3
Pin Description
Pi n Number Pin Name Pin Function
1,4 IN, /IN Differential Inputs: This input pair is the differential signal input to the device.
Inputs accept AC- -or DC coupled signals as small as 100mV (200mV
pp). Each
pin terminates to a V
T pin through 50Ω. Note that these inputs will default to an
indeterminate state if left open. Please refer to the "Input Interface Applications"
section for more details.
2 VT Input Termination Center Tap: Each side of the differential input pair termina- tes
to a VT pin. The VT pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
3 VREF-AC Reference Voltage: This output biases to V
CC–1.2V. It is used when AC-
coupling the inputs (IN, /IN). For AC-coupled applications, connect V
REF AC - to the
VT pin and bypass with a 0.01µF low ESR capacitor to V
CC. Maximum
sink/source current is 1.5mA. See “Input Interface Applications” section for ±
more details.
5,8,13,16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and
place as close to each VCC pin as possible.
12,11
9,10
Q0, /Q0,
Q1, /Q1
Differential Outputs: These 100K LVPECL compatible output pairs are the -
precision, low skew copies of the inputs. Unused output pairs may be left open.
Terminate with 50Ω to VCC–2V. See “LVPECL Output Interface Application
section for more details.
6,7,14,15 GND,
Exposed Pad
Ground. GND and exposed pad must both be connected to the same ground
plane.


Specyfikacje produktu

Marka: Microchip
Kategoria: nieskategoryzowany
Model: SY89851U

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