Instrukcja obsługi Microchip SY88053CL

Microchip nieskategoryzowany SY88053CL

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SY88053CL/SY88063CL
Evaluation Board
1G to 12.5G Limiting Post Amplifiers with
Programmable Decision Threshold (053CL)
Digital Offset Correction (063CL)
Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • San - - http://www.micrel.com
August 20, 2013
Revision 1.0
General Description
The SY88053CL/063CL evaluation board enables fast and
thorough evaluation of the SY88053CL/063CL limiting
amplifiers.
The board is an easy supply design, driven - - -to use, single
by a high speed pattern generator to a 50- and terminated Ω
scope. The board features simple user adjustability of the
LOS board threshold, through the adjustment of an on-
potentiometer and different setting options selections using
jumpers.
The SY88053CL/063CL are part of Micrel’s industry
leading family of ultra speed fiber- -small high -o ptic ICs.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
• M - ulti rate operation from 1.0625Gbps to 12.5Gbps
• External crosspoint adjustment (053CL)
• Digital offset correction (063CL)
• Wide differential input range (5mVPP to 1800mVPP)
• -a a Wide SD de ssert or LOS ssert threshold range
− 3mVPP to 30mVPP
− 4dB typical electrical hysteresis
• e-a Fast SD assert and LOS d ssert times
− 75ns typical; 120ns maximum
• Selectable LOS or SD status signal indicator
• − Selectable RXOUT+/RXOUT polarity (053CL)
• - - TTL compatible JAM input with internal pull up
• - Low noise CML data inputs with integrated 50Ω
termination impedance to internal reference VREF
• - Low noise CML data outputs with integrated 50Ω
termination impedance
− 25ps typical rise/fall times
• W ± ide range power supply: 3.3V 10%
• − Industrial temp range: 40°C to +85°C
• x Available in a tiny 3mm 3mm QFN package
Applications
• Asymmetrical/Symmetrical 10GEPON and XGPON
• 10G Gigabit Ethernet,
• 8G and 10G Fibre Channel
• SONET OC192; SDH STM64
• WDM/DWDM systems
• OBSAI, CPRI
Markets
• PON/FTTx
• Telecom, datacom/enterprise
• Storage area networks
• - High performance computing
• Wireless
Micrel, Inc.
SY88053CL/SY88063CL Evaluation Board
August 20
, 2 2013 Revision 1.0
Ordering Information( )
1
Ordering Part Number PCB Revision Description
SY88053CL SY88053CL-EVAL -EB-1-A Evaluation board for 1.0625G to 12.5G Limiting Post Amplifier with Programmable
Decision Threshold
SY88063CL SY8805-EVAL 3CL-EB-1-A Evaluation board for 1.0625G to 12.5G Limiting Post Amplifier with Digital Offset
Correction
Note:
1. SY88063CL. The same evaluation board (SY88053CL A) is used for both SY88053CL and - -1-EB
Evaluation Board
Micrel, Inc.
SY88053CL/SY88063CL Evaluation Board
August 20
, 3 2013 Revision 1.0
Evaluation Board Description
The SY88053CL/063CL evaluation board is designed to
operate with a single 3.3V ±10% power supply and is
configured with AC-coupled inputs and outputs. The high-
speed input and output signals are brought out to SMA
connectors through matched length AC coupled differential -
traces.
AC- Coupled Input
The AC re internally biased as follows:-coupled inputs a
For the SY88053CL, the internal 50 resistors are Ω
terminated to VCC −1.2V. For the SY88063CL, the internal
50Ω resistors are terminated to VCC . −0.9V
AC- Coupled Output
The board is configured with AC coupled outputs to -
interface directly with 50 load equipment inputs. If only Ω
one output is used, the unused complementary output
must be terminated with 50 to ground.Ω
Coupling Capacitors Selection
The coupling cap should be carefully selected, acitor value
especially when the same circuit is used for multi-rate
applications, for instance in 1G/10G or 2.5G/10G PON
applications.
The RC time constant created by the capacitor and the
input termination resistor can cause a baseline DC droop if
the selected capacitor value is too small for the data rate
and the data pattern contains long strings of Consecutive
Identical Digits (CID). It can also cause pattern dependent
jitter if the selected value is too large for the data rate.
Choose the coupling cap to get an optimized acitor value
low-frequency cutoff that minimizes the two problems
together.
For 1G/10G or 2.5G/10G application range, 10nF would be
a good choice, but o optimize the coupling be sure t
capacitor value for specific application. the
Measurements
Evaluating RXOUT+ and RXOUT−
−
−
−−
1. Set a DC power supply to +3.3V and turn it off.
2. Connect the positive lead to VCC post and the negative
lead to GND post.
3. input to Connect the /EN GND (jumper between pin1
and pin 2 of JP2) to enable the RXOUT+ and RXOUT −
output buffers.
4. For SY88063CL: Do not install jumpers on JP1 and
JP3.
5. For SY88053CL: Connect VTHN and VTHP to GND
(install jumper on JP1 and jumper between pins 1 and
2 of JP3) to turn off the crosspoint adjustment or
connect VTHN to VTHREF (jumper between pin 2 and
pin 3 of JP3) and apply a voltage to VTHP (JP1 open)
to adjust the eye crossing (start with a voltage close to
VTHREF).
6. Set the desired frequency on a pattern generator with
amplitude between 5mVPP and 1800mVPP. Typical data
patterns are 27 −1 or 223 , −1 PRBS patterns
depending on the application. Because the inputs to
the board are AC-coupled, the voltage offset of the
pattern generator is not significant can be set and
between GND and VCC.
7. Connect the pattern generator with differential outputs
as a data source to the RXIN+ and RXIN inputs on −
the SY88053CL/063CL evaluation board. Use
matched length differential cables.
8. Turn the power supply on.
9. Observe RXOUT+ and RXOUT outputs on a 50− Ω
input scope.
Adjusting Crosspoint (053CL)
1. As mentioned in step bove, to adjust crosspoint, 5 a
move the jumper on JP3 to connect VTHN to
VTHREF.
2. Remove the jumper from JP1.
3. Apply a 1.25V DC voltage to TP1 and adjust it slightly
to set crossing at 50%, higher or lower.
Digital Offset Correction (DOC) (063CL)
The DOC circuit correct for internal offset and may not be s
able to fully compensate for offset that external circuits
and/or driving devices such TIA may impose at the inp uts
of the device.
To enable the DOC function in the SY88063CL, leave JP1
open or apply a high signal to DOC_EN (pin 2 of JP1).
To disable the DOC function, install a jumper on JP1.
LOS/SD Timing Measurements
The board comes with 10nF coupling capacitors at the
inputs and outputs. To minimize the effect of the input RC
time constant on the signal delay from the SMA connectors
to the input of the device the caps must be replace with ,
lower values caps (100pF or lower). This delay may
increase the measured LOS/SD assert/de assert time.-
LOS Hysteresis Measurements
The SY88053CL/063CL evaluation board provides a
potentiometer (R2) to allow for convenient adjustment of
SD/LOSLVL without the need for an extra power supply.
SD/LOSLVL taps off a potentiometer connected between
VCC and VREF. VREF is an internal reference voltage of
approximately VCC −1.3V. LOSLVLSo, SD/ can be set to
any voltage between VCC Vand CC −1.3V, as specified in
the dataSY88053CL and SY88063CL sheets. The
potentiometer creates a voltage divider. Thus the
SD/LOSLVL can be calculated Equation 1.using

Specyfikacje produktu

Marka: Microchip
Kategoria: nieskategoryzowany
Model: SY88053CL

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