Instrukcja obsługi Microchip PIC24FJ128GB202

Microchip Niesklasyfikowane PIC24FJ128GB202

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12-Bit A

D Converter

w/Threshold Detect

Section 51. 12-Bit A/D Converter with Threshold Detect

HIGHLIGHTS

This section of the manual contains the following major topics:

51.1 Introduction ................................................................................................................. 51-2

51.2 A/D Terminology and Conversion Sequence .............................................................. 51-4

51.3 Registers ..................................................................................................................... 51-6

51.4 A/D Module Configuration......................................................................................... 51-19

51.5 Initialization ............................................................................................................... 51-23

51.6 Controlling the Sampling Process............................................................................. 51-24

51.7 Controlling the Conversion Process.......................................................................... 51-24

51.8 A/D Results Buffer..................................................................................................... 51-30

51.9 Extended DMA Operations ....................................................................................... 51-34

51.10 Threshold Detect Operation...................................................................................... 51-37

51.11 Conversion Sequence Examples.............................................................................. 51-44

51.12 A/D Sampling Requirements..................................................................................... 51-53

51.13 Transfer Functions .................................................................................................... 51-54

51.14 A/D Accuracy/Error ...................................................................................................51-56

51.15 Operation During Sleep and Idle Modes................................................................... 51-56

51.16 Effects of a Reset ...................................................................................................... 51-57

51.17 Register Maps ........................................................................................................... 51-58

51.18 Electrical Specifications.............................................................................................51-59

51.19 Design Tips ...............................................................................................................51-60

51.20 Related Application Notes......................................................................................... 51-61

51.21 Revision History ........................................................................................................ 51-62

PIC24F Family Reference Manual

51.1 INTRODUCTION

The PIC24F 12-bit A/D Converter has the following key features:

• Successive Approximation Register (SAR) Conversion

• Conversion Speeds of up to 200 ksps

• Up to 32 Analog Input Channels (Internal and External)

• Multiple Internal Reference Input Channels

• External Voltage Reference Input Pins

• Unipolar Differential Sample-and-Hold (S/H) Amplifier

• Automated Threshold Scan and Compare Operation to Pre-Evaluate Conversion Results

• Selectable Conversion Trigger Source

• Fixed-Length (one word per channel), Configurable Conversion Result Buffer

• Four Options for Results Alignment

• Configurable Interrupt Generation

• DMA Operation with Indirect Address Generation

• Operation During CPU Sleep and Idle modes

The 12-bit A/D Converter module is an enhanced version of the 10-bit module offered in some

PIC24 devices. Both modules are Successive Approximation Register (SAR) Converters at their

cores, surrounded by a range of hardware features for flexible configuration. This version of the

module extends functionality by providing 12-bit resolution, a wider range of automatic sampling

options, tighter integration with other analog modules, such as the CTMU, and a configurable

results buffer. This module also includes a unique Threshold Detect feature that allows the

module itself to make simple decisions based on the conversion results.

As before, an internal Sample-and-Hold (S/H) amplifier acquires a sample of an input signal, then

holds that value constant during the conversion process. A combination of input multiplexers

selects the signal to be converted from up to 32 analog inputs, both external (analog input pins)

and internal (e.g., on-chip voltage references and other analog modules). The whole multiplexer

path includes provisions for differential analog input, although, with a limited number of negative

input pins. The sampled voltage is held and converted to a digital value, which strictly speaking,

represents the ratio of that input voltage to a reference voltage. Configuration choices allow

connection of an external reference or use of the device power and ground (AVDD and AVSS).

Reference and input signal pins are assigned differently depending on the particular device.

An array of timing and control selections allow the user to create flexible scanning sequences. Con-

versions can be started individually by program control, continuously free-running or triggered by

selected hardware events. A single channel may be repeatedly converted. Alternate conversions

may be performed on two channels, or any or all of the channels may be sequentially scanned and

converted according to a user-defined bit map. The resulting conversion output is a 12-bit digital

number, which can be signed or unsigned, left or right justified. (In some devices, a user-selectable

resolution of 10 bits is available; in other devices, 12-bit resolution is the only option available.)

Conversions are automatically stored in a dedicated buffer, allowing for multiple successive

readings to be taken before software service is needed. The buffer can be configured to function

as a FIFO buffer or as a channel indexed buffer. In FIFO mode, the buffer can be split into two

equal sections for simultaneous conversion and read operations. In Indexed mode, the buffer can

use the Threshold Scan feature to determine if a conversion meets specific, user-defined criteria,

storing or discarding the converted value as appropriate, and then set semaphore flags to

indicate the event. This allows conversions to occur in low-power modes when the CPU is

inactive, waking the device only when specific conditions have occurred.

The module sets its interrupt flag after a selectable number of conversions, when the buffer can be

read, or after a successful Threshold Detect comparison. After the interrupt, the sequence restarts

at the beginning of the buffer. When the interrupt flag is set, according to the earlier selection, scan

selections and the Output Buffer Pointer return to their starting positions.

A simplified block diagram for the module is shown in Figure 51-1.

Section 51. 12-Bit A/D Converter with Threshold Detect

12-Bit A

D Converter

w/Threshold Detect

Figure 51-1: 12-Bit A/D Converter Block Diagram

Comparator

12-Bit SAR Conversion Logic

VREF+

DAC

AN(n-1)

ANn(1)

AN8

AN9

AN4

AN5

AN6

AN7

AN0

AN1

AN2

AN3

VREF-

Sample Control

S/H

AVSS

AVDD

ADC1BUF0:

ADC1BUFn(3)

AD1CON1

AD1CON2

AD1CON3

AD1CHS

AD1CHITL

AD1CHITH

Control Logic

Data Formatting

Input MUX Control

Conversion Control

Pin Config. Control

Internal Data Bus

V +V - RR

MUX AMUX B

VINH

VINL

VINH

VINL

VR+

VR-

VR Select

VBG (2)

VBG/6(2)

AD1CSSL

Note 1: Up to 32 analog channels may be implemented, depending on the particular device family and individual device pin

count. Some or all of these may be external channels, depending on the device. Refer to the specific device data

sheet for details.

2: Internal analog channels are implemented with different options in different device families. Refer to the specific

device data sheet for details.

3: The conversion buffer will always be at least the same size (in words) as the number of external channels, rounded

up to the next greater even number. Refer to the specific device data sheet for the exact number.

CTMU(2)

DDCORE

(2)

AVSS(2)

AVDD(2)

AD1CON5

VBG/2(2)

VBG

AD1CSSH

AD1CTMENL

AD1CTMENH

AD1DMBUF

AD1CON4

Specyfikacje produktu

Marka:	Microchip
Kategoria:	Niesklasyfikowane
Model:	PIC24FJ128GB202

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