Instrukcja obsługi Microchip PIC16F1829

Microchip Niesklasyfikowane PIC16F1829

Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Microchip PIC16F1829 (14 stron) w kategorii Niesklasyfikowane. Ta instrukcja była pomocna dla 2 osób i została oceniona przez 2 użytkowników na średnio 4.5 gwiazdek

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 2012 Microchip Technology Inc. DS01450A-page 1

AN1450

INTRODUCTION

In this application note, a PIC10F322 is being used to

implement a delay block/debouncer. The delay can be

set between 2 µs and 193 µs. This can be used

effectively as a noise discriminator, or for switch

debouncing.

When used as a delay block, the application can be

used to fix low-level timing issues on signals. When

used as a debouncer, it can debounce signals from a

mechanical switch so that a clean signal can feed other

circuitry.

The application makes use of the Configurable Logic

Cell (CLC) peripheral to produce fast switching on the

output (if desired). If the same application were written

using port logic only, there would be multiple instruction

cycles before the output would change in response to

an input. Using the CLC the signal can be routed

directly and only have propagation and gate delay

between the input and output signals. In order to get

the highest performance possible from the application,

it has been written in assembly.

The code has been written in-line (without subroutines)

to maximize switching performance of the application.

The code uses only 43 locations of program memory

(512 available), and one byte of RAM.

This application note was developed using a

PIC10F322 demo board (part # AC103011). Language

tool versions: MPASMWIN.exe v5.45, mplink.exe

v4.43, mplib.exe v4.43.

DELAY SETTINGS AND VALUES

Delays can be set between 2 µs and 193 µs in 750 ns

increments (using the 16 MHz internal clock). Delays

can easily be made longer if desired, by reducing the

clock speed or increasing the size of the delay loop.

Enabling/disabling of delays is configured in the code

by commenting/uncommenting the following lines of

code:

Independent rising and falling edge delay times can be

set in the following lines of code:

Voltage: 2.3 to 5.5V.

CALCULATING DELAY VALUES

There are two options for setting delay values, and they

are determined by commenting/uncommenting the

MS_DELAY definition:

1. 1 millisecond step size – this is useful for switch

debouncing with recommended settings of

FALLING_EDGE_DELAY = 100 ms, and

RISING_EDGE_DELAY disabled.

Delays are set in milliseconds.

2. 750 ns step size

With the part running at 16 MHz, there are 250 ns per

instruction cycle. The delay loop takes three instruction

cycles to execute, so 750 ns are added for each

incremental change in the countdown timer. There are

approximately eight instructions (2 µs) that will be

executed between an input change and an output

change, if the shortest possible delay is selected

(RISING_EDGE_DELAY or FALLING_EDGE_DELAY

= 1).

Operating current: ~ 2.4 mA (but can be reduced with

lower clock speed).

MODES OF OPERATION

Rising Edge Delay

In this mode, only the rising edge has a delay, and the

falling edge will drop immediately.

Author: Stephen Allen

Microchip Technology Inc.

;; 2 lines below enable rising and falling

edge delays

#define RISING_EDGE_DELAY

#define FALLING_EDGE_DELAY

;; specify length of falling and rising edge

below

RISE_EDGE_DELAY equ 0x01

FALL_EDGE_DELAY equ 0x01

#define MS_DELAY

;#define MS_DELAY

delay = 2 µs + (delay_value x 750 ns)

Delay Block/Debouncer

AN1450

DS01450A-page 2  2012 Microchip Technology Inc.

Falling Edge Delay (Pulse Extender)

In this mode, the rising edge will come up immediately,

and the falling edge will be delayed.

Rising and Falling Edge Delay

In this mode, the user has the option to set independent

rising and falling edge values.

The diagram below (Figure 1) shows the relationship

between the rising and falling edges. Signal edges are

marked for reference in the source assembly code

(delay.asm).

FIGURE 1: MEASUREMENT OF RISING AND FALLING EDGE DELAYS

 2012 Microchip Technology Inc. DS01450A-page 3

AN1450

When falling edge delay is not selected, the signal is

routed through the CLC and has approximately 50 ns

of propogation delay. Figure 2 shows the input and

output signals.

FIGURE 2: PROPAGATION DELAY

BLOCK DIAGRAM

With the CLC block configured as a pass-through, it is

possible to quickly route signals to the output when no

delay is desired, and the PIC® device core (port

function) will create edge delays when desired. The

MUX (CLC1CON, LC1OE) selects whether the pin is

driven by the CLC or by the port logic (Figure 3).

FIGURE 3: BLOCK DIAGRAM – MUX

BETWEEN PORT AND CLC

LOGIC BLOCK

Port Pin

Input

Port Pin

Output

PIC® Device Core PORTA<2>

CLC Block

configured as

pass-through

CLC1CON, LC1OE

Specyfikacje produktu

Marka:	Microchip
Kategoria:	Niesklasyfikowane
Model:	PIC16F1829

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