Instrukcja obsługi Microchip MCP3913
Microchip
nieskategoryzowany
MCP3913
Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Microchip MCP3913 (24 stron) w kategorii nieskategoryzowany. Ta instrukcja była pomocna dla 4 osób i została oceniona przez 2.5 użytkowników na średnio 4.5 gwiazdek
Strona 1/24
2013-2020 Microchip Technology Inc. DS20005227C-page 1
MCP3913
Features
• Six Synchronous Sampling 24-Bit Resolution
Delta-Sigma A/D Converters
• 94.5 dB SINAD, -107 dBc Total Harmonic
Distortion (THD) (up to 35th Harmonic), 112 dBFS
SFDR for Each Channel
• Enables 0.1% Typical Active Power Measurement
Error Over a 10,000:1 Dynamic Range
• Advanced Security Features:
- 16-Bit Cyclic Redundancy Check (CRC)
Checksum on All Communications for Secure
Data Transfers
- 16-Bit CRC Checksum and Interrupt Alert for
Register Map Configuration
- Register Map Lock with 8-Bit Secure Key
• 2.7V-3.6V AVDD, DVDD
• Programmable Data Rate Up to 125 ksps:
- 4 MHz Maximum Sampling Frequency
- 16 MHz Maximum Master Clock
• Oversampling Ratio Up to 4096
• Ultra-Low Power Shutdown Mode with <10 µA
• -122 dB Crosstalk Between Channels
• Low Drift 1.2V Internal Voltage Reference:
9 ppm/°C
• Differential Voltage Reference Input Pins
• High-Gain PGA on Each Channel (up to 32 V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-Bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication Time with Dedicated
16/32-Bit Modes
• Available in a 40-Lead UQFN and 28-Lead SSOP
Packages
• Extended Temperature Range: -40°C to +125°C
Description
The MCP3913 is a 3V six-channel Analog Front End
(AFE), containing six synchronous sampling Delta-
Sigma, Analog-to-Digital Converters (ADC), six PGAs,
phase delay compensation block, low-drift internal volt-
age reference, Digital Offset and Gain Error Calibration
registers and high-speed 20 MHz SPI-compatible serial
interface.
The MCP3913 ADCs are fully configurable with features
such as: 16/24-bit resolution, Oversampling Ratio
(OSR) from 32 to 4096, gain from 1x to 32x, indepen-
dent shutdown and Reset, dithering and auto-zeroing.
The communication is largely simplified with 8-bit
commands, including various continuous Read/Write
modes and 16/24/32-bit data formats that can be
accessed by the Direct Memory Access (DMA) of an 8,
16 or 32-bit MCU, and with the separate Data Ready
pin that can directly be connected to an Interrupt
Request (IRQ) input of an MCU.
The MCP3913 includes advanced security features to
secure the communications and the configuration set-
tings, such as a CRC-16 checksum on both serial data
outputs and static register map configuration. It also
includes a register map lock through an 8-bit secure key
to stop unwanted WRITE commands from processing.
The MCP3913 is capable of interfacing with a variety of
voltage and current sensors, including shunts, Current
Transformers, Rogowski coils and Hall effect sensors.
Applications
• Polyphase Energy Meters
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
3V Six-Channel Analog Front End
MCP3913
DS20005227C-page 2 2013-2020 Microchip Technology Inc.
Package Type
Functional Block Diagram
2
35
3
4
5
6
13 14 15 16 17
27
26
25
24
23
38 37 36 34
CH0+
CH0-
CH1+
CH2+
CH1-
CH4-
CH5+
NC
CH5-
NC
DGND
DVDD
SDI
SDO
RESET
AVDD
EP
41
7
CH2-
8
CH3-
18
NC
19
NC
28
29
33
SCK
32
CS
OSC2
DR
9
CH3+
22
31
OSC1/CLKI
20
NC
AGND
1
10
11 12
CH4+
40 39
DVDD
AVDD
DGND
30
21
AGND
REFIN-
DGND
NC
NC
NC
NC
MCP3913
5x5 UQFN*
* Includes Exposed Thermal Pad (EP); see Table 3-1.
REFIN+/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
CH0+
CH0-
CH3+
CH4+
CH4-
CH5-
CH5+
REFIN+/OUT
CH1-
CH1+
CH2+
CH2-
CH3-
DVDD
RESET
SDI
DGND
NC
DR
DGND
AGND
REFIN-
SDO
SCK
CS
OSC2
OSC1/CLKI
MCP3913
SSOP
OUT
AMCLK
DMCLK/DRCLK
REFIN+/OUT
REFIN-
POR
AVDD
Monitoring
Vref+Vref-
VREFEXT
Voltage
Reference
Vref
+
-
Xtal Oscillator
MCLK OSC1
OSC2
Digital SPI
Interface
Clock
Generation
DMCLK OSR<2:0>
PRE<1:0>
ANALOG DIGITAL
SDO
SDI
SCK
DR
RESET
CS
AGND DGND
AV DD DVDD
CH0+
CH0- -
+
PGA
OSR/2-
PHASE1 <11:0>
MOD<3:0>
'6
'6
'6
'6'6
Modulator
+
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
X
DATA_CH0<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH1+
CH1- -
+
PGA
OSR/2
MOD<7:4>
'6
'6
'6
'6'6
Modulator
+
OFFCAL_CH1
<23:0>
GAINCAL_CH1
<23:0>
X
DATA_CH1<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH2+
CH2- -
+
PGA
OSR/2-
PHASE1 <23:12>
MOD<11:8>
'6
'6
'6
'6'6
Modulator
+
+
+
++
OFFCAL_CH2
<23:0>
GAINCAL_CH2
<23:0>
X
DATA_CH2<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH3+
CH3- -
+
PGA
OSR/2
MOD<15:12>
'6
'6
'6
'6'6
Modulator
+
+
+
++
OFFCAL_CH3
<23:0>
GAINCAL_CH3
<23:0>
X
DATA_CH3<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH4+
CH4- -
+
PGA
OSR/2-
PHASE0<11:0>
MOD<19:16>
'6
'6
'6
'6'6
Modulator
+
+
+
++
OFFCAL_CH4
<23:0>
GAINCAL_CH4
<23:0>
X
DATA_CH4<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
CH5+
CH5- -
+
PGA
OSR/2
MOD<23:20>
'6
'6
'6
'6'6
Modulator
+
+
+
++
OFFCAL_CH5
<23:0>
GAINCAL_CH5
<23:0>
X
DATA_CH5<23:0>
)
)
)
))
SINC3+
SINC1
Phase
Shifter
Offset
Cal.
Gain
Cal.
POR
DVDD
Monitoring
2013-2020 Microchip Technology Inc. DS20005227C-page 3
MCP3913
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
VDD ..................................................................... -0.3V to 4.0V
Digital inputs and outputs w.r.t. A GND................. -0.3V to 4.0V
Analog input w.r.t. AGND.........................................-2V to +2V
VREF input w.r.t. AGND .............................. -0.6V to V
DD + 0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................1.5 kV, 300V
ESD on all other pins (HBM,MM)........................... 2 kV, 300V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other condi-
tions, above those indicated in the operational listings
of this specification, is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
1.1 Electrical Specifications
TABLE 1-1: ANALOG SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
DD = DVDD = 3V; MCLK = 4 MHz;
PRE[1:0] = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, DITHER[1:0] = 11; BOOST[1:0] = 10, V
CM = 0V;
TA= -40°C to +125°C; V
IN = -0.5 dBFS @ 50/60 Hz on all channels.
Characteristic Sym. Min. Typ. Max. Units Conditions
ADC Performance
Resolution
(no missing codes)
24 — — bits OSR = 256 or greater
Sampling Frequency fS(DMCLK) — 1 4 MHz For maximum condition,
BOOST[1:0] = 11
Output Data Rate f
D(DRCLK) — 4 125 ksps For maximum condition,
BOOST[1:0] = 11, OSR = 32
Analog Input Absolute
Voltage on CHn+/- Pins,
n Between 0 and 5
CHn+/- -1 — +1 V All analog input channels
measured to AGND
Analog Input
Leakage Current
IIN — ±1 — nA RESET[5:0] = 111111,
MCLK running continuously
Differential Input
Voltage Range
(CHn+ – CHn-) -600/GAIN — +600/GAIN mV VREF = 1.2V, proportional to VREF
Offset Error VOS -2 0.2 2 mV Note 5
Offset Error Drift — 0.5 — µV/°C
Note 1: Dynamic performance specified at -0.5 dB below the maximum differential input value,
VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz, V
REF = 1.2V. See Section 4.0 “Terminology and Formulas” for
definition. This parameter is established by characterization and not 100% tested.
2: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[5:0] = 000000,
RESET[5:0] = 000000, VREFEXT = 0, CLKEXT = 0.
3: For these operating currents, the following Configuration bit settings apply: SHUTDOWN[5:0] = 111111,
VREFEXT = 1, CLKEXT = 1.
4: Measured on one channel versus all others channels. The average of crosstalk performance over all
channels (see Figure 2-32 for individual channel performance).
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting; see Section 2.0 “Typical
Performance Curves” for typical performance.
6: Outside of this range, ADC accuracy is not specified. An extended input range of ±2V can be applied
continuously to the part with no damage.
7: For proper operation and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency
defined in Table 5-2, as a function of the BOOST and PGA settings chosen. MCLK can take larger values as
long as the prescaler settings (PRE[1:0]) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
Specyfikacje produktu
| Marka: | Microchip |
| Kategoria: | nieskategoryzowany |
| Model: | MCP3913 |
Potrzebujesz pomocy?
Jeśli potrzebujesz pomocy z Microchip MCP3913, zadaj pytanie poniżej, a inni użytkownicy Ci odpowiedzą
Instrukcje nieskategoryzowany Microchip
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
Instrukcje nieskategoryzowany
- nieskategoryzowany Ideal
- nieskategoryzowany Fontastic
- nieskategoryzowany Fuxtec
- nieskategoryzowany GA.MA
- nieskategoryzowany First Alert
- nieskategoryzowany Sennheiser
- nieskategoryzowany Kärcher
- nieskategoryzowany Schatten Design
- nieskategoryzowany Whirlwind
- nieskategoryzowany Dynacord
- nieskategoryzowany Altrad
- nieskategoryzowany LEDs-ON
- nieskategoryzowany Flame
- nieskategoryzowany Cylinda
- nieskategoryzowany Trijicon
Najnowsze instrukcje dla nieskategoryzowany
28 Października 2024
28 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024