Instrukcja obsługi Microchip MCP18480

Microchip nieskategoryzowany MCP18480

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฀ 2002-2012 Microchip Technology Inc. DS20091C-page 1
MCP18480
Features
• Allows safe board removal and insertion from a
live backplane
• Accurate (<1.5%) internal voltage reference for
fault detection and precision timing
• Programmable foldback current limiting
• Programmable circuit breaker current limiting
• Auto restart option for all faults
• Adjustable Undervoltage lockout thresholds
• Adjustable Overvoltage protection threshold
• Adjustable Power Good delay
• Configurable Power Good output polarity
• Low-side drive of an external N-channel FET
CMOS Technology
• High-Voltage Operation
• Temperature range: Industrial (I): -40°C to +85°C
Packaging
• 20-lead SSOP
Package Type
Description
The MCP18480 is a Hot Swap controller that allows
boards to be safely removed or inserted from an active
backplane using -48V.
When PCBs are inserted into a live backplane, high-
peak or transient currents from the source are gener-
ated due to the charging of the bypass capacitors on
the supply. The high transient currents can destroy
connectors and capacitors. The high inrush current can
pull the input voltage BUS down and reset the system.
The MCP18480 solves this problem by controlling the
slew rate of the backplane voltage to the board so that
these transients are eliminated. This allows boards to
be removed and inserted without causing damage to
connector pins and input bulk capacitors, in addition to
preventing false resets to the other boards on the
backplane.
The MCP18480 can be used in applications in several
areas including:
• Telecom Line Cards
• Network Switches
• Network Routers and Servers
• Base Station Line Cards
• Power-Over-LAN
• Power-Over-MDI
• IP Phone Switches/Routers
• Mid-Span, Power-Over-MDI
Two forms of current limit are provided in the
MCP18480. These are:
• Foldback
• Circuit breaker
The foldback current-limiting circuit uses an external
sense resistor and a voltage that is proportional to the
external MOSFET’s drain voltage. These are used to
keep the MOSFET in its Safe Operating Area (SOA).
If the device remains in current limit for a programmed
time period, the external N-channel FET is turned off.
The option exists to configure the device to automati-
cally restart after a programmed time delay. A program-
mable catastrophic current limit threshold shuts down
the switch (circuit breaker) if excessive current is
sensed due to a short-circuit condition.
2
3
4
5
6
7
8
9
10
1
19
18
16
15
14
13
12
11
17
20
ENABLE
RESTART
UVD
VREFIN
OVO
VFB
PWRGOOD
DRAINTH
SENSE
GATE
CL
ISET
TIMER
RDISCH
VNEG
OVTH
UVTH
UVHYS
VREFOUT
VPOS
MCP18480
SSOP
-48V Hot Swap Controller
MCP18480
DS20091C-page 2 ฀ 2002-2012 Microchip Technology Inc.
Internal comparators are incorporated to add hystere-
sis for adjusting the Undervoltage Lockout (UVLO)
threshold. The external N-channel MOSFET is turned
on when the input is below the user-programmable,
Overvoltage threshold and above the user-
programmable, Undervoltage threshold.
The PWRGOOD pin indicates the status of the
MCP18480 and is active when the device has com-
pleted power-up and the system is not in an Undervolt-
age, Overvoltage or current-limit condition.
PWRGOOD can be externally configured to either
active-high or active-low to accommodate external cir-
cuitry (power supplies) that have either enabling logic.
A block diagram of the MCP18480 is shown below.
MCP18480 Block Diagram
VPOS
UVTH
UVD
OVTH
V
NEG
GATE
VFB
MCP18480
UVHYS
VREFOUT
VREFIN
SENSE TIMER
RDISCH
LATCHOFF
ISET
PWRGOOD
(1)
DRAINTH
12V
Regulator
12V OUT
5V
Reg.
5VOUT
5VOUT
Latch
Undervoltage Active
Overvoltage Active
Current Limit Timer
ENABLE
RESTART
CL
VPOS
OVO
PWRGOOD
Output Block
VNEG
BIAS
Undervoltage
Overvoltage
Current Limit
GATE
Drive
Timer
FET Good
Circuit Breaker
TIMEOUT
Current Limit Feedback
SENSE
Internal
Bias
Generation
Note 1: The PWRGOOD output pin can be either active-high or active-low. This polarity is determined by the
voltage (either the level on the VREFIN pin or level on the VNEG pin) on the ISET pin:
- RConnecting the external ISET resistor to VREFIN configures the PWRGOOD pin as active-low
- RConnecting the external ISET resistor to V
NEG configures the PWRGOOD pin as active-high
(Section 6.8.3)
(Section 6.8.8)
(Section 6.8.2)
(Section 6.8.1)
(Section 6.8.4)
(Section 6.8.9)
(Section 6.8.5)
(Section
6.8.6)
(Section 6.8.7)
2002-2012 Microchip Technology Inc. DS20091C-page 3
MCP18480
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Ambient Temperature under bias........ –40°C to +85°C
Storage Temperature ........................ –65°C to +150°C
Voltage on VPOS with respect to VNEG -0.3V to +15.0V
Voltage on DVTH, UVTH, VFB, OVO and UVHYS pins
with respect to VNEG ..... VNEG – 0.3V to (VPOS + 0.3V)
Voltage on VREFIN, CL, SENSE, DRAINTH, ENABLE
and RESTART pins with respect to V
NEG
........................................................ V
NEG - 0.3V to 6V.
Total Power Dissipation (Note 1) .................... 800 mW
Max. Current out of VNEG pin.............................80 mA
Max. Current into VPOS pin ................................50 mA
Max. Output Current sunk by Gate pin...............80 mA
Max. Output Current sunk by VREFOUT pin .......... 5 mA
Max. Output Current sunk by any other
Output pin.........................................................25 mA
Max. Output Current sourced by Gate pin ........200 µA
Max. Output Current sourced by VREFOUT pin .....5 mA
Max. Output Current sourced by any other
Output pin...........................................................25 mA
Junction to Ambient, JA
(20 pin SSOP Package) Derating ...............108.1C/W
Junction to Case, JC
(20 pin SSOP Package) Derating .................32.2C/W
Lead Temperature, Soldering, 10 seconds ........ 300C
† Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
Note 1: Power Dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, operating temperature: –40 C T A +85C (Industrial),
Supply Current: 5 mA IPOS 25 mA, RISET = 125 k, CBYP = 2 µF.
Param.
No. Parameter Sym Min Typ (1) Max Units Conditions
MD001 Current into shunt regulator
that produces VPOS output volt-
age that meets MD001A speci-
fication
IPOS1 5 — 25 mA ENABLE pin = 5V
5 — 25 ENABLE pin = V NEG
MD001A Regulated Output Voltage
Differential of VPOS to VNEG
VPOS 10.4 12.0 13.4 V See MD001
MD002 VREFOUT pin output voltage V REFOUT 2.463 2.5 2.538 V Load = 50 µA
MD010 VGATE pin output voltage VGATE VPOS - 2 VPOS
-1 V POS V
MD011 Voltage on ISET pin VISET (V REFIN/2) -
0.02
VREFIN/2 (VREFIN/2)
+0.02
V
MD012A Voltage on SENSE pin to
trigger current-limiting
VSENSE 40 50 60 mV VFB = VNEG
MD012B 25 31.0 40 mV V FB = VNEG + 0.25V
MD012C 7 12 17 mV V FB = VNEG + 0.5V
MD013 Undervoltage Threshold UV TH VREFIN
- 0.03
VREFIN VREFIN
+ 0.03
V
MD014A Overvoltage
Threshold
rising OVTH VREFIN
- 0.05
VREFIN VREFIN
+ 0.05
V VREFIN
= 2.5V
MD014B falling OVTH VREFIN
- 0.035
VREFIN
- 0.02
VREFIN
- 0.005
V VREFIN
= 2.5V
MD015 DRAIN Pin Input Threshold
Voltage
VDTH 90 100 130 mV
Note 1: Data in the Typical (“Typ”) column is based on characterization results at +25C. This data is for design guidance only
and is not tested.
2: Negative current is defined as current sourced by the pin.
3: All voltages are with respect to the VNEG pin voltage.

Specyfikacje produktu

Marka: Microchip
Kategoria: nieskategoryzowany
Model: MCP18480

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