Instrukcja obsługi Microchip LAN7801

Microchip Niesklasyfikowane LAN7801

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 2016 Microchip Technology Inc. DS00002054A-page 1

INTRODUCTION

This application note is intended to assist customers in designing a PCB using Microchip’s family of 10/100/1000 Mbps

Ethernet devices. This document provides recommendations regarding PCB layout, a critical component in maintaining

signal integrity and reducing EMI issues. The following topics are covered:

•General PCB Layout Guidelines on page 1

•USB Layout Guidelines on page 5

•Ethernet Layout Guidelines on page 5

•EMI Considerations on page 8

•ESD Considerations on page 9

•Troubleshooting Common Layout Issues on page 10

GENERAL PCB LAYOUT GUIDELINES

Power Supply Consideration

• Ensure adequate power supply ratings. Verify that all power supplies and voltage regulators can supply the

amount of current required.

• Power supply output ripple should be limited to less than 50 mV (less than 10mV for the best performance).

• Noise levels on all power and ground planes should be limited to less than 50mV.

• Ferrite beads should be rated for 4-6 times the amount of current they are expected to supply. Any derating over

temperature should also be accounted for.

Device Decoupling

• Every high-speed semiconductor device on the PCB assembly requires decoupling capacitors. One decoupling

capacitor for every power pin is necessary.

• The decoupling capacitor value is application dependent. Typical decoupling capacitor values may range from

0.001uF to 0.1uF.

• The total decoupling capacitance should be greater than the load capacitance presented to the digital output buf-

fers to prevent noise from being introduced into the supply.

• Typically, Class II dielectric capacitors are chosen for decoupling purposes. The first choice would be an X7R

dielectric ceramic capacitor for it's excellent stability and good package size versus capacitance characteristics.

The designer's second choice may be the X5R dielectric for its excellent stability. However, the X5R may be some-

what limiting in the package size versus capacitance characteristics. Low inductance is of the utmost importance

when considering decoupling capacitor characteristics.

• Each decoupling capacitor should be located as close as possible to the power pin that it is decoupling.

• All decoupling capacitor leads should be as short as possible. The best practice is directly connecting the capaci-

tors to the ground and power pin on top layer. If using vias becomes inevitable, pad-to-via connections should be

less than 10 mils in length. Trace connections should be as wide as possible to lower inductance.

• Strongly consider connecting the ground of all bypass capacitors with two vias to greatly reduce the inductance of

that connection.

AN2054

Gigabit Ethernet Design Guide

Author: Kiet Tran



Microchip Technology Inc.

AN2054

DS00002054A-page 2  2016 Microchip Technology Inc.

PCB Bypassing

• Bypass capacitors should be placed near all power entry points on the PCB. These capacitors absorb the high fre-

quency currents from the high-speed digital load.

• Bypass capacitors should be utilized on all power supply connections and all voltage regulators in the design.

• Bypass capacitor values are application dependent and wi es present in the power ll be dictated by the frequenci

supplies and the load transient amplitude and frequency.

• All bypass capacitor leads should be as short as possible. The best practice is directly connecting the capacitors

to the ground and power pin on top layer. If using vias become inevitable, the via outside the surface mount pad,

pad-to-via connections should be less than 10 mils in length. Trace connections should be as wide as possible to

lower inductance.

• Strongly consider connecting the ground of all bypass capacitors with two vias to greatly reduce the inductance of

that connection.

PCB Bulk Capacitors

• Bulk capacitors must be properly utilized in order to minimize switching noise. Bulk capacitance helps maintain

constant DC voltage and current levels.

• Bulk capacitors should be utilized on all power planes and all voltage regulators in the design.

• All bulk capacitor leads should be as short as possible. The best solution is plane connection vias inside the sur-

face mount pads. When using vias outside the surface mount pads, pad-to-via connections should be less than 10

mils in length. Trace connections should be as wide as possible to lower inductance.

• Good design practices dictate that whenever a ferrite bead is used in the circuit, bulk capacitance should be

placed on each side of the ferrite bead.

• In the case where a ferrite bead is used on the USB connector to filter the VCC, the use of bulk capacitance on the

USB connector side is not recommended. This is an attempt to limit the in-rush current of the USB circuitry. Micro-

chip does recommend the use of a 4.7uF bulk capacitor on the inboard side of the ferrite bead.

FIGURE 1: EXAMPLE PCB BYPASSING TECHNIQUE

 2016 Microchip Technology Inc. DS00002054A-page 3

AN2054

PCB Layer Strategy

• Use at least a 4-layer PCB for all Ethernet LAN designs.

• The typical PCB stack-up uses a signal layer on the top (component side) layer, a solid, contiguous ground plane

layer on Layer 2, a solid power plane layer on Layer 3 and another signal layer on Layer 4. Layer 1 is considered

the prime layer for critical routes and components because of the solid digital ground plane directly beneath it and

Layer 1 also requires no vias to connect components located on Layer 1.

• All PCB traces (especially high-speed and critical signal traces) should be routed on Layer 1 next to the solid, con-

tiguous ground plane layer. These traces must have a continuous reference plane for their entire length of travel.

Avoid signal traces crossing a plane split (Figure 2) as this can cause unpredictable return path currents, and this

would likely result in signal integrity issues as well as creating EMI problems. If crossing splits in the reference

plane are unavoidable, consider adding stitching capacitors.

• The implementation of an Ethernet chassis ground plane separate from the digital ground plane is required.

• Avoid creating ground loops in the PCB design and the system design.

• In order to facilitate routing and minimize signal cross talk issues, adjacent layers in a multi-layer design should be

routed orthogonal.

RECOMMENDED LAYER STACKS LAYOUT

• Four-Layer Board

- Signal 1 (top layer)

- GND

- Power plane/GND

- Signal 2

• Six-Layer Board

- Signal 1 (top layer)

- Power plane/GND

- Signal 2 (best for clock and high speed signals)

- Signal 3 (best for clock and high speed signals)

- GND

- Signal 4

FIGURE 2: EXAMPLE SIGNAL CROSSING PLANE SPLIT

Specyfikacje produktu

Marka:	Microchip
Kategoria:	Niesklasyfikowane
Model:	LAN7801

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